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型式74xx138ICのVerilog-HDLモデルです。


//
// Title        : (138) 3 to 8 Demultiplexer
// File name    : 138.v
// Date         : 2000/12/08  Ver1.0
// Company      : Future Technology Ltd.
//

//----------------------------------------------------------
//  Module
//----------------------------------------------------------
module U138 (
            G1,
            XG2A,
            XG2B,
            I,
            Y
         );

    input           G1;
    input           XG2A;
    input           XG2B;
    input   [2:0]   I;
    output  [7:0]   Y;

//----------------------------------------------------------
//  Using wire
//----------------------------------------------------------
    reg     [7:0]   Y;
//----------------------------------------------------------
//  Using wire
//----------------------------------------------------------
    wire    [5:0]   s_in;


    assign  s_in    = {G1 , XG2A , XG2B , I};

    always@(s_in)begin
        case(s_in[5:0])
            6'b100000   :   Y = 8'b11111110;
            6'b100001   :   Y = 8'b11111101;
            6'b100010   :   Y = 8'b11111011;
            6'b100011   :   Y = 8'b11110111;
            6'b100100   :   Y = 8'b11101111;
            6'b100101   :   Y = 8'b11011111;
            6'b100110   :   Y = 8'b10111111;
            6'b100111   :   Y = 8'b01111111;
            default     :   Y = 8'b11111111;
        endcase
    end

endmodule



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