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型式74xx280ICのVerilog-HDLモデルです。


//
// Title        : (280) 9-Bit Parity Generators/Checkers
// File name    : 280.v
// Date         : 2000/12/08  Ver1.0
// Company      : Future Technology Ltd.
// Writer       : K.Bettou 
//

//-----------------------------------------------------
//  Module
//-----------------------------------------------------

module U280 (
            A,
            B,
            C,
            D,
            E,
            F,
            G,
            H,
            I,
            EVEN,
            ODD
        );

    input       A;
    input       B;
    input       C;
    input       D;
    input       E;
    input       F;
    input       G;
    input       H;
    input       I;
    output      EVEN;
    output      ODD;

//-----------------------------------------------------
//  Using register
//-----------------------------------------------------
    wire        s_odd;


    assign  s_odd = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H ^ I;

    assign  ODD = s_odd;
    assign  EVEN = ~s_odd;

endmodule



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